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| 74ABT162244 16-Bit Buffer/Line Driver with 25 Series Resistors in the Outputs April 1992 Revised March 2002 74ABT162244 16-Bit Buffer/Line Driver with 25 Series Resistors in the Outputs General Description The ABT162244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3STATE control inputs can be shorted together for 8-bit or 16-bit operation. The 25 series resistors in the outputs reduce ringing and eliminate the need for external resistors. Features s Separate control logic for each nibble s 16-bit version of the ABT2244 s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability Ordering Code: Order Number 74ABT162244CSSC 74ABT162244CSSX 74ABT162244CMTD 74ABT162244MTDX Package Number MS48A MS48A MTD48 MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Inputs Outputs (c) 2002 Fairchild Semiconductor Corporation DS010987 www.fairchildsemi.com 74ABT162244 Truth Tables Inputs OE1 L L H Inputs OE3 L L H Inputs OE2 L L H Inputs OE4 L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Outputs I0-I3 L H X O0-O3 L H Z Outputs I8-I11 L H X O8-O11 L H Z Outputs I4-I7 L H X O4-O7 L H Z Outputs I12-I15 L H X O12-O15 L H Z Schematic of each Output Functional Description The ABT162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. www.fairchildsemi.com 2 74ABT162244 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5V -0.5V to 5.5V -0.5V to VCC Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. -500 mA 10V DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.8 1 1 7 -1 -1 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A V A A mA A A mA mA mA mA mA A mA/ 0.1 MHz Max Min Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 12 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 A All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 3) Note 3: Guaranteed, but not tested. 10 -10 -100 -275 50 100 2.0 60 2.0 3.0 3.0 50 0 - 5.5V VOUT = 2.7V; OEn = 2.0V 0 - 5.5V VOUT = 0.5V; OEn = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OEn = VCC All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs OPEN OEn = GND One Bit Toggling, 50% Duty Cycle No Load Max 3 www.fairchildsemi.com 74ABT162244 AC Electrical Characteristics TA = +25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.0 1.5 1.5 1.0 1.0 VCC = +5V CL = 50 pF Typ 2.4 3.2 3.5 4.2 4.2 3.8 Max 3.9 4.7 6.3 6.9 6.7 6.7 1.0 1.0 1.5 1.5 1.0 1.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min Max 3.9 4.7 6.3 6.9 6.7 6.7 ns ns ns Units Capacitance Symbol CIN COUT (Note 4) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 Units pF pF VCC = 0.0V VCC = 5.0V Conditions TA = 25C Note 4: COUT is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT162244 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT162244 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 6 74ABT162244 16-Bit Buffer/Line Driver with 25 Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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